Implementation of Novel Power Efficient AES Design on High Performance FPGA

In the age of Information and Communication Technology (ICT), the globe is much concerned about two major challenges that are secured data transmission and power efficiency. This work highlights both challenges. In this work, we have designed a power-efficient design of the Advanced Encryption Standard (AES) algorithm using the Field Programmable Gate Array (FPGA) device. The implementation of the AES is done on VIVADO Design Suite, and the results are observed on Spartan-7 FPGA. To optimize the power consumption of the AES on the FPGA device, Stub Series Terminated Logic (SSTL) Input Output (IO) is used. IO standards are used in FPGA to match the impedance so that the power consumption is optimized. On analysing the power consumption, it is observed that as the input voltage of the IO standard is increased the Total Power Consumption (TPC) also gets increased. The TPC observed is minimum for SSTL 135 IO and it is maximum for SSTL_18_II IO.