Implementation of High-Performance AES Crypto Processor for Green Communication

The world is intensely concerned about two vital issues in the Information and Communication Technology (ICT) era: energy efficiency and secure data transfer. This paper emphasizes both complications. In the paper, we have implemented a (Field Programmable Gate Array) FPGAbased design of the Advanced Encryption Standard (AES) algorithm that is power-efficient.
The AES is implemented on Xilinx VIVADO, and the results are seen on a Kintex-7 device. LVCMOS (Low voltage complementary metal oxide semiconductor) Input Output (IO) is employed at various clock speeds to improve the power utilization of the AES on the FPGA device. According to the power analysis, the AES design consumes little power at high clock rates since the Total Power Consumption (TPC) declines as clock rates increase.